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FEATURES
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LT3500 Monolithic 2A Step-Down Regulator Plus Linear Regulator/Controller DESCRIPTION
The LT(R)3500 is a current mode PWM step-down DC/DC converter with an internal 2.3A switch. The wide input range of 3V to 40V makes the LT3500 suitable for regulating power from a wide variety of sources, including automotive batteries, 24V industrial supplies and unregulated wall adapters. Resistor-programmable 250kHz to 2.2MHz frequency range and synchronization capability enable optimization between efficiency and external component size. Cycleby-cycle current limit, frequency foldback and thermal shutdown provide protection against a shorted output. The soft-start feature controls the ramp rate of the output voltage, eliminating input current surge during start-up, and also provides output tracking. The LT3500 contains an internal NPN transistor with feedback control which can be configured as a linear regulator or as a linear regulator controller. The LT3500's low current shutdown mode (<12A) enables easy power management in battery-powered systems.
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
Wide Input Range: 3V to 36V Operating, 40V Maximum Short-Circuit Protected Over Full Input Range 2A Output Current Capability Adjustable/Synchronizable Fixed Frequency Operation from 250kHz to 2.2MHz Soft-Start/Tracking Capability Output Adjustable Down to 0.8V Adjustable Linear Regulator/Driver with 13mA Output Capability Power Good Comparator with Complimentary Outputs Low Shutdown Current: 12A Thermally Enhanced 3mm x 3mm DFN or 16-Pin MSOP Package
APPLICATIONS
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Automotive Battery Regulation Industrial Control Wall Transformer Regulation Distributed Power Regulation
TYPICAL APPLICATION
Dual Step-Down Converters
VIN 6V TO 36V 2.2F VIN LT3500 SW SHDN SS 0.47F FB PG PG RT/SYNC LDRV VC LFB 40.2k 8.06k 22F
3500 TA01a
Switching Converter Efficiency
90 85 VOUT1 5V 1A 22F 80 EFFICIENCY (%) 75 70 65 60 VOUT2 = 3.3V AT 1A AC COUPLED 2mV/DIV VOUT1 = 5V AT 1A AC COUPLED 2mV/DIV
Output Voltage Ripple
BST 0.47F 6.8H B240A 42.2k 8.06k
53.6k 330pF
1k 24.9k
55 VOUT2 3.3V 1A 50 0
VIN = 12V IOUT2 = 0A FREQUENCY = 800kHz 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 LOAD CURRENT (A)
3500 TA01b
500ns/DIV
3500 TA01c
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LT3500 ABSOLUTE MAXIMUM RATINGS
(Note 1)
VIN, PG, PG Operating .................................... 40V/-0.3V SW .............................................................................VIN BST ................................................................ 55V/-0.3V BST Pin Above SW....................................................25V LDRV, SHDN ..............................................................15V FB, LFB, RT/SYNC .......................................................5V SS, VC ......................................................................2.5V
Operating Junction Temperature Range LT3500EDD (Note 2) .......................... -40C to 125C LT3500IDD (Note 2) ........................... -40C to 125C LT3500HDD (Note 2).......................... -40C to 150C LT3500EMSE (Note 2)........................ -40C to 125C LT3500IMSE (Note 3) ........................ -40C to 125C LT3500HMSE (Note 2) ....................... -40C to 150C Storage Temperature Range................... -65C to 150C
PIN CONFIGURATION
TOP VIEW VIN SHDN SS PG VC RT/SYNC 1 2 3 4 5 6 13 12 SW 11 BST 10 LDRV 9 LFB 8 FB 7 PG NC1 VIN SHDN SS PG VC RT/SYNC NC8 1 2 3 4 5 6 7 8 TOP VIEW 16 15 14 13 12 11 10 9 NC16 SW BST LDRV LFB FB PG NC9
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DD PACKAGE 12-LEAD (3mm x 3mm) PLASTIC DFN JA = 45C/W, JC(PAD) = 10C/W EXPOSED PAD (PIN 13) IS GND, MUST BE SOLDERED TO PCB
MSE PACKAGE 16-LEAD PLASTIC MSE JA = 45C/W, JC(PAD) = 10C/W EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH LT3500EDD#PBF LT3500IDD#PBF LT3500HDD#PBF LT3500EMSE#PBF LT3500IMSE#PBF LT3500HMSE#PBF TAPE AND REEL LT3500EDD#TRPBF LT3500IDD#TRPBF LT3500HDD#TRPBF LT3500EMSE#TRPBF LT3500IMSE#TRPBF LT3500HMSE#TRPBF PART MARKING* LCRN LCRN LDCY 3500 3500 3500 PACKAGE DESCRIPTION 12-Lead (3mm x 3mm) Plastic DFN 12-Lead (3mm x 3mm) Plastic DFN 12-Lead (3mm x 3mm) Plastic DFN 16-Lead Plastic MSE 16-Lead Plastic MSE 16-Lead Plastic MSE TEMPERATURE RANGE -40C to 125C -40C to 125C -40C to 150C -40C to 125C -40C to 125C -40C to 150C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
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LT3500
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TJ = 25C. VVIN = 15V, VRT/SYNC = 2V, unless otherwise specified.
PARAMETER SHDN Threshold SHDN Source Current SHDN Current Hysterisis Minimum Input Voltage (Note 3) Supply Shutdown Current Supply Quiescent Current FB Voltage FB Bias Current Error Amplifier gm Error Amplifier Source Current Error Amplifier Sink Current Error Amplifier High Clamp Error Amplifier Switching Threshold SS Source Current SS Sink Current SS POR Sink Current (Note 4) SS POR Threshold SS to FB Offset (VSS - VFB) PG/PG Leakage PG/PG Threshold (Rising) PG/PG Hysteresis (Falling) PG Sink Current PG Sink Current RT/SYNC Reference Voltage Switching Frequency VVC = VFS, VSS = 0.4V VFB = 0.9V, VPG/VPG = 40V VPG = 0.4V VPG = 0.4V VPG = 0.4V, VFB = 0.7V VPG = 0.4V, VFB = 0.9V VFB = 0.9V, RRT/SYNC = 15k RRT/SYNC = 90.9k RRT/SYNC = 90.9k RRT/SYNC = 15k VFB = 0.7V, RRT/SYNC = 90.9k VFB = 0.7V, RRT/SYNC = 90.9k VSW = 0V ISW = 2A, VBST = 18V, VFB = 0.7V VBST = 18V, VFB = 0.7V VBST = 18V, VFB = 0.7V ISW = 2A, VBST = 20V, VFB = 0.7V ISW = 2A, VFB = 0.7V
l l l l
ELECTRICAL CHARACTERISTICS
CONDITIONS
MIN
l
TYP 760 2.5 2 2.4 12 2.5
MAX 780 3.5 3.25 2.8 30 3.5 0.816 0.824 150 350 20 22 2.2 1.0 3.75 900 800 150 120 1 0.730 40 750 1100 0.975 550 625 2.8 2500
UNITS mV A A V A mA V V nA mho A A V V A A A mV mV A V mV A A V kHz kHz MHz kHz ns ns
710 1.5 1.25
VSHDN = 0.62V VFB = 0V VSHDN = 0V VFB = 0.9V VVC = 1V VVC = 0.8V to 1.6V, VIN = 3V to 40V VFB = 0.8V, VVC = 1V VVC = 1V, IVC = 10A VFB = 0.6V, VVC = 1V VFB = 1V, VVC = 1V VFB = 0.6V VFB = 0.6V VSS = 0.4V, VFB = 0.9V VFB = 0V, VSS = 2V VFB = 0V, VSS = 2V, Cycle SHDN
l l l l
0.784 0.776 150 12 14 1.8 0.6 2.25 300 400 50 70 0.685 20 250 500 0.75 450 425 2 250
0.8 0.8 50 250 16 18 2.0 0.8 2.75 600 600 100 100 0.1 0.708 30 500 800 0.850 500 500 2.4 140 120 1 450
SYNC Frequency Range Minimum Switch On Time Minimum Switch Off Time Switch Leakage Current Switch Saturation Voltage Switch Peak Current DD Package Switch Peak Current MSE Package Boost Current Minimum Boost Voltage (Note 5)
10 3.5 3.5 3.5 3.7 45 3
A mV A A A A mA V
2.3 2.1 2.3 2.1 20
2.8 2.8 2.9 2.9 30 2.2
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LT3500 ELECTRICAL CHARACTERISTICS
PARAMETER LFB Voltage LFB Line/Load Regulation SS to LFB Offset (VSS - VLFB) LFB Bias Current LDRV Dropout (VVIN - VLDRV) LDRV Maximum Current CONDITIONS VLDRV = VLFB VVIN = 3V to 40V, VLDRV = VLFB VSS = 0.8V, VLDRV = VLFB VLFB = 0.8V VLDRV = 3V, ILDRV = 5mA VLDRV = 0V
l l l l
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TJ = 25C. VVIN = 15V, VRT/SYNC = 2V, unless otherwise specified.
MIN 0.784 0.776 90 0.8 9 TYP 0.8 0.8 115 115 1.2 13 MAX 0.816 0.824 140 300 1.6 18 UNITS V V mV nA V mA
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note2: The LT3500EDD/LT3500EMSE is guaranteed to meet performance specifications from 0C to 125C junction temperature. Specifications over the -40C to 125C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LT3500IDD/LT3500IMSE is guaranteed over the full -40C to 125C operating junction temperature range. The LT3500HDD/LT3500HMSE is guaranteed over the full -40C to 150C operating junction temperature range. High junction temperatures degrade operating lifetimes. Operating lifetime is derated at junction temperatures greater than 125C. Note 3: Minimum input voltage is defined as the voltage where internal bias lines are regulated so that the reference voltage and oscillator remain constant. Actual minimum input voltage to maintain a regulated output
will depend upon output voltage and load current. See Applications Information. Note 4: An internal power-on reset (POR) latch is set on the positive transition of the SHDN pin through its threshold. The output of the latch activates a current source on the SS pin which typically sinks 600A, discharging the SS capacitor. The latch is reset when the SS pin is driven below the soft-start POR threshold or the SHDN pin is taken below its threshold. Note 5: This is the minimum voltage across the boost capacitor needed to guarantee full saturation of the internal power switch. Note 6: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed the maximum operating junction temperature when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability.
TYPICAL PERFORMANCE CHARACTERISTICS
Feedback Voltage vs Temperature
0.820 0.815 0.810 VOLTAGE (V) 0.805 0.800 0.795 0.790 0.785 0.780 -50 -25 0 25 50 75 100 125 150 TEMPERATURE (C)
3500 G01
RT/SYNC Voltage vs Temperature
1.10 1.08 1.06 1.04 VOLTAGE (V) 1.02 1.00 0.98 0.96 0.94 0.92 0.90 -50 -25 0 25 50 75 100 125 150 TEMPERATURE (C)
3500 G02
Shutdown Threshold and Minimum Input Voltage vs Temperature
3.0 2.5 MINIMUM INPUT VOLTAGE
RRT/SYNC = 90.9k VOLTAGE (V) 2.0 1.5 1.0 RRT/SYNC = 15k 0.5 0 -50 -25
FB LFB
SHUTDOWN THRESHOLD
0
25 50 75 100 125 150 TEMPERATURE (C)
3500 G03
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LT3500 TYPICAL PERFORMANCE CHARACTERISTICS
Shutdown Input Currents vs Temperature
6 5 4 3 VSHDN = 0.7V 2 1 0 -50 -25 VSHDN = 0.9V CURRENT (A) 15.0 TRANSCONDUCTANCE (mhos) 25 50 75 100 125 150 TEMPERATURE (C)
3500 G05
Shutdown Quiescent Current vs Temperature
400 350 300 250 200 150
Error Amplifier gm vs Temperature
12.5 10.0 7.5 5.0 2.5 0 -50 -25
CURRENT (A)
0
25 50 75 100 125 150 TEMPERATURE (C)
3500 G04
0
100 -50 -25
0
25 50 75 100 125 150 TEMPERATURE (C)
3500 G06
Soft-Start Source Current vs Temperature
3.5 3.3 3.1 2.9 VOLTAGE (mV) CURRENT (A) 2.7 2.5 2.3 2.1 1.9 1.7 1.5 -50 -25 0 25 50 75 100 125 150 TEMPERATURE (C)
3500 G07
Soft-Start Feedback Offset vs Temperature
150 0.95 0.90 125 VOLTAGE (V) LFB 100 FB 75 0.85 0.80 0.75 0.70 0.65 0.60 0.55 50 -50 -25 0 25 50 75 100 125 150 TEMPERATURE (C)
3500 G08
VC Switching Threshold vs Temperature
0.50 -50 -25
0
25 50 75 100 125 150 TEMPERATURE (C)
3500 G09
Power Good Thresholds vs Temperature
0.75 0.74 0.73 0.72 VOLTAGE (V) 0.71 0.70 0.69 0.68 0.67 0.66 0.65 -50 -25 0 25 50 75 100 125 150 TEMPERATURE (C)
3500 G10
Power Good Sink Currents vs Temperature
1000 900 800 PG FREQUENCY (kHz) 600 580 560 540 520 500 480 460 440 420 0 25 50 75 100 125 150 TEMPERATURE (C)
3500 G11
Frequency vs Temperature
RRT/SYNC = 90.9k
RISING EDGE CURRENT (A)
700 600 500 400 300 200 100 0 -50 -25 PG
FALLING EDGE
400 -50 -25
0
25 50 75 100 125 150 TEMPERATURE (C)
3500 G12
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LT3500 TYPICAL PERFORMANCE CHARACTERISTICS
Peak Switch Current vs Temperature
3.5 3.4 3.3 3.2 CURRENT (A) 3.1 3.0 2.9 2.8 2.7 2.6 2.5 -50 -25 0 25 50 75 100 125 150 TEMPERATURE (C)
3500 G13
LDRV Short-Circuit Current vs Temperature
20 19 18 100 90 80 DUTY CYCLE (%) 70 60 50 40 30 20 10 0 25 50 75 100 125 150 TEMPERATURE (C)
3500 G14
External Sync Duty Cycle Range vs External Sync Frequency
MAXIMUM DUTY CYCLE
MSE PACKAGE CURRENT (mA)
17 16 15 14 13 12 11 10 -50 -25
TA = 25C
DD PACKAGE
MINIMUM DUTY CYCLE
0 250
2250 750 1750 1250 SYNCHRONIZATION FREQUENCY (kHz)
3500 G15
Minimum Switching Times
300 275 250 225 TIME (ns) 200 175 150 125 100 75 50 -50 -25 0 25 50 75 100 125 150 TEMPERATURE (C)
3500 G16
Frequency vs RRT/SYNC
2500 2250 2000 FREQUENCY (kHz) 1750 1500 1250 1000 750 500 250 0 0 20 40 60 80 100 120 140 160 180 200 RRT/SYNC (k)
3500 G17
Switch Saturation Voltage vs Switch Current
TA = 25C SWITCH SATURATION VOLTAGE (mV) 600 500 400 300 -50C 200 100 150C 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 SWITCH CURRENT (A)
3500 G18
MINIMUM ON TIME
MINIMUM OFF TIME
25C
Boost Current vs Switch Current
50 45 40 BOOST CURRENT (mA) 35 30 25 20 15 10 5 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 SWITCH CURRENT (A)
3500 G19
Minimum Boost Voltages vs Temperature
2.7 2.5 BOOST VOLTAGE (V) 2.3 2.1 1.9 1.7 1.5 -50 -25 MINIMUM BOOST FOR SWITCH SATURATION INPUT VOLTAGE (V) 8 7 6 5 4 3 2 1 0 0 25 50 75 100 125 150 TEMPERATURE (C)
3500 G20
Minimum Input Voltage
TA = 25C
150C -50C
VOUT1 = 5V
VOUT1 = 3.3V
25C
fSW = 1MHz L = 3.3H 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 LOAD CURRENT (A)
3500 G21
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LT3500 TYPICAL PERFORMANCE CHARACTERISTICS
LDRV Dropout Voltage vs Temperature
1.50 1.45 1.40 OUTPUT VOLTAGE (V) 1.35 VOLTAGE (V) 1.30 1.25 1.20 1.15 1.10 1.05 1.00 -50 -25 0 0 25 50 75 100 125 150 TEMPERATURE (C)
3500 G22
Switcher Dropout Operation
6 5 4 VVOUT1 = 3.3V 3 2 1 IVOUT1 = 1A TA = 25C VVOUT1 = 5V FREQUENCY (kHz) 2500 2250
Inductor Value for 2A Maximum Load Current (VOUT1 = 3.3V, IRIPPLE = 250mA)
TA = 25C L = 1H 2000 1750 1500 1250 1000 750 500 L = 4.7H L = 6.8H L = 10H 5 10 15 20 25 30 INPUT VOLTAGE (V) 35 40 L = 3.3H L = 1.5H L = 2.2H
ILDRV = 5mA
2.5
3.0
3.5 4.0 4.5 INPUT VOLTAGE (V)
5.0
5.5
3500 G23
250
3500 G24
PIN FUNCTIONS
VIN: The VIN pin powers the internal control circuitry and is monitored by an undervoltage comparator. The VIN pin is also connected to the collectors of the internal power NPN switch and linear output NPN. The VIN pin has high dI/dt edges and must be decoupled to ground close to the pin of the device. SHDN: The SHDN pin is used to shut down the LT3500 and reduce quiescent current to a typical value of 12A. The accurate 0.76V threshold and input current hysteresis can be used as an undervoltage lockout, preventing the regulator from operating until the input voltage has reached a predetermined level. Force the SHDN pin above its threshold or let it float for normal operation. SS: The SS pin is used to control the slew rate of the output of both the switching and linear regulators. A single capacitor from the SS pin to ground determines the regulators' ramp rate. For soft-start details see the Applications Information section. PG: The power good pin is an open-collector output that sinks current when the FB or LFB falls below 90% of its nominal regulating voltage. For VIN above 2V, its output state remains true, although during SHDN, VIN undervoltage lockout, or thermal shutdown, its current sink capability is reduced VC: The VC pin is the output of the error amplifier and the input to the peak switch current comparator. It is normally used for frequency compensation, but can also be used as a current clamp or control loop override. If the error amplifier drives VC above the maximum switch current level, a voltage clamp activates. This indicates that the output is overloaded and current to be pulled from the SS pin reducing the regulation point. RT/SYNC: This RT/SYNC pin provides two modes of setting the constant switch frequency. Connecting a resistor from the RT/SYNC pin to ground will set the RT/SYNC pin to a typical value of 1V. The resultant switching frequency will be set by the resistor value. The minimum value of 15k and maximum value of 200k set the switching frequency to 2.5MHz and 250kHz respectively.
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LT3500 PIN FUNCTIONS
Driving the RT/SYNC pin with an external clock signal will synchronize the switch to the applied frequency. Synchronization occurs on the rising edge of the clock signal after the clock signal is detected. Each rising clock edge initiates an oscillator ramp reset. A gain control loop servos the oscillator charging current to maintain a constant oscillator amplitude. Hence, the slope compensation remains unchanged. If the clock signal is removed, the oscillator reverts to resistor mode and reapplies the 1V bias to the RT/SYNC pin after the synchronization detection circuitry times out. The clock source impedance should be set such that the current out of the RT/SYNC pin in resistor mode generates a frequency roughly equivalent to the synchronization frequency. Floating or holding the RT/SYNC pin above 1.1V will not damage the device, but will halt oscillation. PG: The power good bar pin is an open-collector output that sinks current when the FB or LFB rises above 90% of its nominal regulating voltage. FB: The FB pin is the negative input to the switcher error amplifier. The output switches to regulate this pin to 0.8V with respect to the exposed ground pad. Bias current flows out of the FB pin. LFB: The LFB pin is the negative input to the linear error amplifier. The LDRV pin servo's to regulate this pin to 0.8V with respect to the exposed ground pad. Bias current flows out of the LFB pin. LDRV: The LDRV pin is the emitter of an internal NPN that can be configured as an output of a linear regulator or as the drive for an external NPN high current regulator. Current flows out of the LDRV pin when the LFB pin voltage is below 0.8V. The LDRV pin has a typical maximum current capability of 13mA. BST: The BST pin provides a higher than VIN base drive to the power NPN to ensure a low switch drop. A comparator to VIN imposes a minimum off time on the SW pin if the BST pin voltage drops too low. Forcing a SW off time allows the boost capacitor to recharge. SW: The SW pin is the emitter of the on-chip power NPN. At switch off, the inductor will drive this pin below ground with a high dV/dt. An external catch diode to ground, close to the SW pin and respective VIN decoupling capacitor's ground, must be used to prevent this pin from excessive negative voltages. Exposed Pad: GND. The Exposed Pad is the only ground connection for the device. The Exposed Pad should be soldered to a large copper area to reduce thermal resistance. The GND pin also serves as small-signal ground. For ideal operation all small-signal ground paths should connect to the GND pin at a single point, avoiding any high current ground returns. NC Pins (MSE Package Only): No Connection. The NC pins are electrically isolated from the LT3500. The NC pins may be connected to PCB traces to aid PCB layout.
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VIN
BLOCK DIAGRAM
C1 2.5A 2A 0.8V INTERNAL REGULATOR AND REFERENCES
GND
+ +
LDRV VOUT2 R3 LFB R4 C5 D2
SHDN
+ - +
S Q R DRIVER CIRCUITRY SW OSCILLATOR AND AGC
0.76V
RT/SYNC
R5
C3 POWER ON RESET S Q R PRE THERMAL OVERLOAD
C4
2.75A
+ + -
R6
SS
+
0.7V
C2
100mV
-
LFB
Figure 1. LT3500 Block Diagram
+
VC
-
115mV
SLOPE COMPENSATION
+ SS -
C6
D1
L1 VOUT1 R1 FB SS PG R2 C7
0.8V 100mV
+ - -
PG
3500 BD
LT3500
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LT3500 OPERATION
The LT3500 is a constant frequency, current mode buck converter with an internal 2.3A switch plus a linear regulator with 13mA output capability. Control of both outputs is achieved with a common SHDN pin, internal regulator, oscillator, undervoltage detect, soft-start, thermal shutdown and power-on reset. If the SHDN pin is taken below its 0.8V threshold, the LT3500 will be placed in a low quiescent current mode. In this mode the LT3500 typically draws 12A from the VIN pin. When the SHDN pin is floated or driven above 0.76V, the internal bias circuits turn on generating an internal regulated voltage, 0.8(VFB) and 1V(RT/SYNC) references, and a POR signal which sets the soft-start latch. As the RT/SYNC pin reaches its 1V regulation point, the internal oscillator will start generating a clock signal at a frequency determined by the resistor from the RT/SYNC pin to ground. Alternatively, if a synchronization signal is detected by the LT3500 at the RT/SYNC pin, a clock signal will be generated at the incoming frequency on the rising edge of the synchronization pulse. In addition, the internal slope compensation will be automatically adjusted to prevent subharmonic oscillation during synchronization. The LT3500 is a constant frequency, current mode stepdown converter. Current mode regulators are controlled by an internal clock and two feedback loops that control the duty cycle of the power switch. In addition to the normal error amplifier, there is a current sense amplifier that monitors switch current on a cycle-by-cycle basis. This technique means that the error amplifier commands current to be delivered to the output rather than voltage. A voltage fed system will have low phase shift up to the resonant frequency of the inductor and output capacitor, then an abrupt 180 shift will occur. The current fed system will have 90 phase shift at a much lower frequency, but will not have the additional 90 shift until well beyond the LC resonant frequency. This makes it much easier to frequency compensate the feedback loop and also gives much quicker transient response. During power up, the POR signal sets the soft-start latch, which discharges the SS pin to ensure proper start-up operation. When the SS pin voltage drops below 100mV, the VC pin is driven low disabling switching and the softstart latch is reset. Once the latch is reset the soft-start capacitor starts to charge with a typical value of 2.75A. As the voltage rises above 100mV on the SS pin, the VC pin will be driven high by the error amplifier. When the voltage on the VC pin exceeds 0.8V, the clock set-pulse sets the driver flip-flop which turns on the internal power NPN switch. This causes current from VIN, through the NPN switch, inductor and internal sense resistor, to increase. When the voltage drop across the internal sense resistor exceeds a predetermined level set by the voltage on the VC pin, the flip-flop is reset and the internal NPN switch is turned off. Once the switch is turned off the inductor will drive the voltage at the SW pin low until the external Schottky diode starts to conduct, decreasing the current in the inductor. The cycle is repeated with the start of each clock cycle. However, if the internal sense resistor voltage exceeds the predetermined level at the start of a clock cycle, the flip-flop will not be set resulting in a further decrease in inductor current. Since the output current is controlled by the VC voltage, output regulation is achieved by the error amplifier continually adjusting the VC pin voltage. The error amplifier is a transconductance amplifier that compares the FB voltage to either the SS pin voltage minus 100mV or an internally regulated 800mV, whichever is lowest. Compensation of the loop is easily achieved with a simple capacitor or series resistor/capacitor from the VC pin to ground. Since the SS pin is driven by a constant current source, a single capacitor on the soft-start pin will generate controlled linear ramp on the output voltage. If the current demanded by the output exceeds the maximum current dictated by the VC pin clamp, the SS pin will be discharged, lowering the regulation point until the output voltage can be supported by the maximum current. When overload is removed, the output will soft-start from the overload regulation point.
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LT3500 OPERATION
VIN undervoltage detection or thermal shutdown will set the soft-start latch, resulting in a complete soft-start sequence. The switch driver operates from either the VIN or BST voltage. An external diode and capacitor are used to generate a drive voltage higher than VIN to saturate the output NPN and maintain high efficiency. In addition to the switching regulator, the LT3500 contains a NPN linear regulator with a 0.8V reference, and 13mA current capability. The 0.8 reference will track the SS pin in the same manner as the switching regulator. The linear output can also be configured to drive an external NPN to provide a linear regulator with higher current capability. A power good comparator with 30mV of hysteresis trips when both FB and LFB are above 90% of the 0.8V reference. The PG output is an open collector NPN that is off when the output is in regulation allowing a resistor to pull the PG pin to a desired voltage. The PG output is an opencollector NPN that is on when the output is in regulation providing either drive for an output disconnect transistor or inverted power good logic.
APPLICATIONS INFORMATION
Choosing the Output Voltage The output voltage is programmed with a resistor divider between the output and the FB pin. Choose the 1% resistors according to: R1= R2 VOUT1 -1 0.8V maximum recommended frequency can be approximated by the equation: Frequency (Hz) = VOUT1 + VD 1 * VIN - VSW + VD tON(MIN)
R2 should be 10.0k or less to avoid bias current errors. Reference designators refer to the Block Diagram in Figure 1. Choosing the Switching Frequency The LT3500 switching frequency is set by resistor R5 in Figure 1. The RT/SYNC pin is internally regulated at 1V. Setting resistor R5 sets the current in the RT/SYNC pin which determines the oscillator frequency as illustrated in Figure 2. The switching frequency is typically set as high as possible to reduce overall solution size. The LT3500 employs techniques to enhance dropout at high frequencies but efficiency and maximum input voltage decrease due to switching losses and minimum switch on times. The
where VD is the forward voltage drop of the catch diode (D1 Figure 1), VSW is the voltage drop of the internal switch, and tON(MIN) is the minimum on time of the switch, all at maximum load current.
2500 2250 2000 FREQUENCY (kHz) 1750 1500 1250 1000 750 500 250 0 0 20 40 60 80 100 120 140 160 180 200 RRT/SYNC (k)
3500 F02
Figure 2. Frequency vs RT/SYNC Resistance
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LT3500 APPLICATIONS INFORMATION
The following example along with the data in Table 1 illustrates the tradeoffs of switch frequency selection. Example. VIN = 25V, VOUT1 = 3.3V, IOUT1 = 2.0A, Temperature = 0C to 85C tON(MIN) = 185ns (85C from Typical Characteristics graph), VD = 0.6V, VSW = 0.4V (85C) Max Frequency = RT/SYNC ~ 49.9k Frequency 820kHz Input Voltage Range Once the switching frequency has been determined, the input voltage range of the regulator can be determined. The minimum input voltage is determined by either the LT3500's minimum operating voltage of ~2.8V or by its maximum duty cycle. The duty cycle is the fraction of time that the internal switch is on during a clock cycle. The maximum duty cycle can be determined from the clock frequency and the minimum off time from the typical characteristics graph. This leads to a minimum input voltage of: VIN(MIN) = VOUT1 + VD - VD + VSW DCMAX 3.3 + 0.6 1 * ~ 835kHz 25 - 0.4 + 0.6 185ns where VSW is the voltage drop of the internal switch, and DCMAX = 1 - tOFF(MIN) * Frequency. Figure 3 shows a typical graph of minimum input voltage vs load current for 3.3V and 5V applications. The maximum input voltage is determined by the absolute maximum ratings of the VIN and BST pins and by the frequency and minimum duty cycle. The minimum duty cycle is defined as: DCMIN = tON(MIN) * Frequency Maximum input voltage as: VIN(MAX) =
8 7 INPUT VOLTAGE (V) 6 5 4 3 2 VOUT1 = 5V START-UP VOUT1 = 5V RUNNING VOUT1 = 3.3V START-UP VOUT1 = 3.3V RUNNING 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 LOAD CURRENT (A)
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VOUT1 + VD - VD + VSW DCMIN
fSW = 1MHz L = 3.3H
Figure 3. Minimum Input Voltage vs Load Current
Table 1. Efficiency and Size Comparisons for Different RRT/SYNC Values, VOUT1 = 3.3V
FREQUENCY 2.5MHz 2.0MHz 1.5MHz 1.0MHz 500kHz RT/SYNC 15k 20k 24.9k 40.2k 90.9k EFFICIENCY 73.6 81.5 84.5 87.3 88.9 VIN(MAX) 12 14 18 28 36 L 1 1.5 2.2 3.3 4.7 C 10 10 10 22 47 C + L AREA (mm2) 24 24 24 34 40
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Note that the LT3500 will regulate if the input voltage is taken above the calculated maximum voltage as long as maximum ratings of the VIN and BST pins are not violated. However operation in this region of input voltage will exhibit pulse skipping behavior. Example: VOUT1 = 3.3V, IOUT1 = 1A, Frequency = 1MHz, Temperature = 25C, VSW = 0.3V, VD = 0.4V, tON(MIN) = 150ns, tOFF(MIN) = 110ns DCMAX = 1- (110ns)1MHz = 89% VIN(MIN) = 3.3 + 0.4 - 0.4 + 0.3 = 4.06V 0.89 3.3 + 0.4 - 0.4 + 0.3 = 24.57V 0.15 For applications with a duty cycle of about 50%, the inductor value should be chosen to obtain an inductor ripple current less than 40% of peak switch current. Of course, such a simple design guide will not always result in the optimum inductor for your application. A larger value provides a slightly higher maximum load current, and will reduce the output voltage ripple. If your load is lower than 1.5A, then you can decrease the value of the inductor and operate with higher ripple current. This allows you to use a physically smaller inductor, or one with a lower DCR resulting in higher efficiency. The current in the inductor is a triangle wave with an average value equal to the load current. The peak switch current is equal to the output current plus half the peak-to peak inductor ripple current. The LT3500 limits its switch current in order to protect itself and the system from overload faults. Therefore, the maximum output current that the LT3500 will deliver depends on the current limit, the inductor value, switch frequency, and the input and output voltages. The inductor is chosen based on output current requirements, output voltage ripple requirements, size restrictions and efficiency goals. When the switch is off, the inductor sees the output voltage plus the catch diode drop. This gives the peak-to-peak ripple current in the inductor: IL =
DCMIN = tON(MIN) * Frequency = 15% VIN(MAX) =
Inductor Selection and Maximum Output Current A good first choice for the inductor value is: (V - V )* V L = IN OUT1 OUT1 VIN * f where f is frequency in MHz and L is in H. With this value the maximum load current will be ~2A, independent of input voltage. The inductor's RMS current rating must be greater than your maximum load current and its saturation current should be about 30% higher. To keep efficiency high, the series resistance (DCR) should be less than 0.05.
(1- DC)( VOUT1 + VD )
L*f
where f is the switching frequency of the LT3500 and L is the value of the inductor. The peak inductor and switch current is: ISW(PK) =ILPK =IOUT1 + IL 2
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To maintain output regulation, this peak current must be less than the LT3500's switch current limit, ILIM. ILIM is guaranteed to be greater than 2.3A over the entire duty cycle range. The maximum output current is a function of the chosen inductor value: IOUT1(MAX) =ILIM - IL I =2.3 - L 2 2
2500 2250 2000 FREQUENCY (kHz) 1750 1500 1250 1000 750 500 250 5 10 15 20 25 30 INPUT VOLTAGE (V) 35 40 L = 3.3H L = 4.7H L = 6.8H L = 2.2H L = 1H L = 1.5H
If the inductor value is chosen so that the ripple current is small, then the available output current will be near the switch current limit. One approach to choosing the inductor is to start with the simple rule given above, look at the available inductors and choose one to meet cost or space goals. Then use these equations to check that the LT3500 will be able to deliver the required output current. Note again that these equations assume that the inductor current is continuous. Discontinuous operation occurs when IOUT1 is less than IL/2 as calculated above. Figure 4 illustrates the inductance value needed for a 3.3V output with a maximum load capability of 2A. Referring to Figure 4, an inductor value between 3.3H and 4.7H will be sufficient for a 15V input voltage and a switch frequency of 750kHz. There are several graphs in the Typical Performance Characteristics section of this data sheet that show inductor selection as a function of input voltage and switch frequency for several popular output voltages and output ripple currents. Also, low inductance may result in discontinuous mode operation, which is okay, but further reduces maximum load current. For details of maximum output current and discontinuous mode operation, see Linear Technology Application Note 44. Finally, for duty cycles greater than 50% (VOUT1/VIN > 0.5), there is a minimum inductance required to avoid subharmonic oscillations. See Application Note 19 for more information.
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Figure 4. Inductor Values for 2A Maximum Load Current (VOUT1 = 3.3V, IRIPPLE = 1A)
Input Capacitor Selection Bypass the input of the LT3500 circuit with a 4.7F or higher ceramic capacitor of X7R or X5R type. A lower value or a less expensive Y5V type can be used if there is additional bypassing provided by bulk electrolytic or tantalum capacitors. The following paragraphs describe the input capacitor considerations in more detail. Step-down regulators draw current from the input supply in pulses with very fast rise and fall times. The input capacitor is required to reduce the resulting voltage ripple at the LT3500 and to force this very high frequency switching current into a tight local loop, minimizing EMI. The input capacitor must have low impedance at the switching frequency to do this effectively, and it must have an adequate ripple current rating. A conservative value is the RMS input current is given by: ICIN(RMS) = IOUT1 VOUT1 * ( VIN - VOUT1 ) VIN
0.5
<
IOUT1 2
and is largest when VIN = 2VOUT1 (50% duty cycle).
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The frequency, VIN to VOUT1 ratio, and maximum load current requirement of the LT3500 along with the input supply source impedance, determine the energy storage requirements of the input capacitor. Determine the worstcase condition for input ripple current and then size the input capacitor such that it reduces input voltage ripple to an acceptable level. Typical values for input capacitors run from 10F at low frequencies to 2.2F at higher frequencies. The combination of small size and low impedance (low equivalent series resistance or ESR) of ceramic capacitors make them the preferred choice. The low ESR results in very low voltage ripple and the capacitors can handle plenty of ripple current. They are also comparatively robust and can be used in this application at their rated voltage. X5R and X7R types are stable over temperature and applied voltage, and give dependable service. Other types (Y5V and Z5U) have very large temperature and voltage coefficients of capacitance, so they may have only a small fraction of their nominal capacitance in your application. While they will still handle the RMS ripple current, the input voltage ripple may become fairly large, and the ripple current may end up flowing from your input supply or from other bypass capacitors in your system, as opposed to being fully sourced from the local input capacitor. An alternative to a high value ceramic capacitor is a lower value along with a larger electrolytic capacitor, for example a 1F ceramic capacitor in parallel with a low ESR tantalum capacitor. For the electrolytic capacitor, a value larger than 10F will be required to meet the ESR and ripple current requirements. Because the input capacitor is likely to see high surge currents when the input source is applied, tantalum capacitors should be surge rated. The manufacturer may also recommend operation below the rated voltage of the capacitor. Be sure to place the 1F ceramic as close as possible to the VIN and GND pins on the IC for optimal noise immunity. A final caution regarding the use of ceramic capacitors for input bypassing. A ceramic input capacitor can combine with stray inductance to form a resonant tank circuit. If power is applied quickly (for example, by plugging the circuit into a live power source) this tank can ring, doubling the input voltage and damaging the LT3500. The solution is to either clamp the input voltage or dampen the tank circuit by adding a lossy capacitor in parallel with the ceramic capacitor. For details see Application Note 88. Output Capacitor Selection Typically step-down regulators are easily compensated with an output crossover frequency that is 1/10 of the switching frequency. This means that the time that the output capacitor must supply the output load during a transient step is ~2 or 3 switching periods. With an allowable 5% drop in output voltage during the step, a good starting value for the output capacitor can be expressed by: C VOUT1 = Example: VOUT1 = 3.3V, Frequency = 1MHz, Max Load Step = 2A C VOUT1 = 2 = 12F 1MHz * 0.05 * 3.3 Max Load Step Frequency * 0.05 * VOUT1
The calculated value is only a suggested starting value. Increase the value if transient response needs improvement or reduce the capacitance if size is a priority. The output capacitor filters the inductor current to generate an output with low voltage ripple. It also stores energy in order to satisfy transient loads and to stabilize the LT3500's control loop. The switching frequency of the LT3500 determines
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the value of output capacitance required. Also, the current mode control loop doesn't require the presence of output capacitor series resistance (ESR). For these reasons, you are free to use ceramic capacitors to achieve very low output ripple and small circuit size. Estimate output ripple with the following equations: VRIPPLE = IL 8 * Frequency * COUT1 The high performance (low ESR), small size and robustness of ceramic capacitors make them the preferred type for LT3500 applications. However, all ceramic capacitors are not the same. As mentioned above, many of the high value capacitors use poor dielectrics with high temperature and voltage coefficients. In particular, Y5V and Z5U types lose a large fraction of their capacitance with applied voltage and temperature extremes. Because the loop stability and transient response depend on the value of COUT1, you may not be able to tolerate this loss. Use X7R and X5R types. You can also use electrolytic capacitors. The ESRs of most aluminum electrolytics are too large to deliver low output ripple. Tantalum and newer, lower ESR organic electrolytic capacitors intended for power supply use, are suitable and the manufacturers will specify the ESR. The choice of capacitor value will be based on the ESR required for low ripple. Because the volume of the capacitor determines its ESR, both the size and the value will be larger than a ceramic capacitor that would give you similar ripple performance. One benefit is that the larger capacitance may give better transient response for large changes in load current. Catch Diode The diode D1 conducts current only during switch off time. Use a Schottky diode to limit forward voltage drop to increase efficiency. The Schottky diode must have a peak reverse voltage that is equal to regulator input voltage and sized for average forward current in normal operation. Average forward current can be calculated from: ID(AVG) = IOUT1 * ( VIN - VOUT1) VIN
For ceramic capacitors and, VRIPPLE = IL * ESR For electrolytic (tantalum and aluminum) where IL is the peak-to-peak ripple current in the inductor. The RMS content of this ripple is very low, and the RMS current rating of the output capacitor is usually not of concern. Another constraint on the output capacitor is that it must have greater energy storage than the inductor; if the stored energy in the inductor is transferred to the output, you would like the resulting voltage step to be small compared to the regulation voltage. For a 5% overshoot, this requirement becomes: I COUT1 > 10 * L LIM VOUT1
2
Finally, there must be enough capacitance for good transient performance. The last equation gives a good starting point. Alternatively, you can start with one of the designs in this data sheet and experiment to get the desired performance. This topic is covered more thoroughly in the section on loop compensation.
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The only reason to consider a larger diode is the worstcase condition of a high input voltage and shorted output. With a shorted condition, diode current will increase to a typical value of 3A, determined by the peak switch current limit of the LT3500. This is safe for short periods of time, but it would be prudent to check with the diode manufacturer if continuous operation under these conditions can be tolerated. BST Pin Considerations The capacitor and diode tied to the BST pin generate a voltage that is higher than the input voltage. In most cases a 0.47F capacitor and fast switching diode (such as the CMDSH-3 or FMMD914) will work well. Almost any type of film or ceramic capacitor is suitable, but the ESR should be <1 to ensure it can be fully recharged during the off time of the switch. The capacitor value can be approximated by: C BST = 50 * VOUT1 - VBST(MIN) * f where IOUT1(MAX) is the maximum load current, and VBST(MIN) is the minimum boost voltage to fully saturate the switch. Figure 5 shows four ways to arrange the boost circuit. The BST pin must be more than 2.2V above the SW pin for full efficiency. Generally, for outputs of 3.3V and higher the standard circuit (Figure 5a) is the best. For outputs between 2.8V and 3.3V, replace the D2 with a small Schottky diode such as the PMEG4005. For lower output voltages the boost diode can be tied to the input (Figure 5b). The circuit in Figure 5a is more efficient because the BST pin current comes from a lower voltage source. Figure 5c shows the boost voltage source from the linear output that is set to greater than 2.5V (any available DC sources that are greater than 2.5V is sufficient). The highest efficiency is attained by choosing the lowest boost voltage above 2.5V. You must also be sure that the maximum voltage at the BST pin is less than the maximum specified in the Absolute Maximum Ratings section.
(
IOUT1(MAX) * DC
)
VIN
VIN LT3500
LDRV BST C3 SW D1 D2 VOUT1
VIN
VIN LT3500
LDRV BST
D2
C3 SW D1 VBST - VSW = VIN VBST(MAX) = 2 *VIN VOUT1
VBST - VSW = VOUT1 VBST(MAX) = VIN + VOUT1
(5a)
(5b)
VIN
VIN LT3500
LDRV D2 BST C3 SW D1
VOUT2
VIN
VIN LT3500
LDRV D2 BST SW D1 VX > VIN + 3V VOUT1
VOUT1 VBST - VSW = VX VBST(MAX) = VX
VBST - VSW = VOUT2 VBST(MAX) = VIN + VOUT2 VOUT2 2.5V
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(5c)
(5d)
Figure 5. BST Pin Considerations
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The boost circuit can also run directly from a DC voltage that is higher than the input voltage by more than 2.5V, as in Figure 5d. The diode is used to prevent damage to the LT3500 in case VX is held low while VIN is present. The circuit eliminates a capacitor, but efficiency may be lower and dissipation in the LT3500 may be higher. Also, if VX is absent, the LT3500 will still attempt to regulate the output, but will do so with very low efficiency and high dissipation because the switch will not be able to saturate, dropping 1.5V to 2V in conduction. The minimum input voltage of an LT3500 application is limited by the minimum operating voltage (<2.8V) and by the maximum duty cycle as outlined above. For proper start-up, the minimum input voltage is also limited by the boost circuit. If the input voltage is ramped slowly, or the LT3500 is turned on with its SS pin when the output is already in regulation, then the boost capacitor may not be fully charged. Because the boost capacitor is charged with the energy stored in the inductor, the circuit will rely on some minimum load current to get the boost circuit running properly. This minimum load will depend on input and output voltages and on the arrangement of the boost circuit. The Typical Performance Characteristics section shows plots of the minimum load current to start and to run as a function of input voltage for 3.3V and 5V outputs. In many cases the discharged output capacitor will present a load to the switcher which will allow it to start. The plots show the worst-case situation where VIN is ramping very slowly. Use a Schottky diode for the lowest start-up voltage.
LT3500 CURRENT MODE POWER STAGE gm = 3mho SW VOUT1 R1 VC CC RC CF 4M ERROR AMP gm = 250mhos FB 0.8V C1 R2 TANTALUM OR POLYMER C1 CPL ESR
Frequency Compensation The LT3500 uses current mode control to regulate the output. This simplifies loop compensation. In particular, the LT3500 does not require the ESR of the output capacitor for stability so you are free to use ceramic capacitors to achieve low output ripple and small circuit size. Frequency compensation is provided by the components tied to the VC pin. Generally a capacitor and a resistor in series to ground determine loop gain. In addition, there is a lower value capacitor in parallel. This capacitor is not part of the loop compensation but is used to filter noise at the switching frequency. Loop compensation determines the stability and transient performance. Designing the compensation network is a bit complicated and the best values depend on the application and in particular the type of output capacitor. A practical approach is to start with one of the circuits in this data sheet that is similar to your application and tune the compensation network to optimize the performance. Stability should then be checked across all operating conditions, including load current, input voltage and temperature. The LT1375 data sheet contains a more thorough discussion of loop compensation and describes how to test the stability using a transient load. Figure 6 shows an equivalent circuit for the LT3500 control loop. The error amp is a transconductance amplifier with finite output impedance. The power section, consisting of the modulator, power switch, and inductor, is modeled as a transconductance amplifier generating an output
Figure 6. Model for Loop Response
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CERAMIC
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LT3500 APPLICATIONS INFORMATION
current proportional to the voltage at the VC pin. Note that the output capacitor integrates this current, and that the capacitor on the VC pin (CC) integrates the error amplifier output current, resulting in two poles in the loop. In most cases a zero is required and comes from either the output capacitor ESR or from a resistor in series with CC. This simple model works well as long as the value of the inductor is not too high and the loop crossover frequency is much lower than the switching frequency. A phase lead capacitor (CPL) across the feedback divider may improve the transient response. Synchronization The RT/SYNC pin can be used to synchronize the LT3500 to an external clock source. Driving the RT/SYNC resistor with a clock source triggers the synchronization detection circuitry. Once synchronization is detected, the rising edge of SW will be synchronized to the rising edge of the RT/SYNC pin signal. An AGC loop will adjust slope compensation to avoid subharmonic oscillation. The synchronizing clock signal input to the LT3500 must have a frequency between 250kHz and 2.5MHz, a duty cycle between 20% and 80%, a low state below 0.5V and a high state above 1.6V. Synchronization signals outside of these parameters will cause erratic switching behavior. The RT/SYNC resistor should be set such that the free running frequency ((VRT/SYNC - VSYNCLO)/RRT/SYNC) is approximately equal to the synchronization frequency. If the synchronization signal is halted, the synchronization detection circuitry will timeout in typically 10s at which time the LT3500 reverts to the free-running frequency based on the current through RT/SYNC. If the RT/SYNC pin is held above 1.1V at any time, switching will be disabled. If the synchronization signal is not present during regulator start-up (for example, the synchronization circuitry is powered from the regulator output) the RT/SYNC pin must see an equivalent resistance to ground between 15k and 200k until the synchronization circuitry is active for proper start-up operation. If the synchronization signal powers up in an undetermined state (VOL, VOH, Hi-Z), connect the synchronization clock to the LT3500 as shown in Figure 7. The circuit as shown will isolate the synchronization signal when the output voltage is below 90% of the regulated output. The LT3500 will start-up with a switching frequency determined by the resistor from the RT/SYNC pin to ground.
LDRV LT3500 PG RT/SYNC VCC SYNCHRONIZATION CIRCUITRY CLK
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Figure 7. Synchronous Signal Powered from Regulator's Output
If the synchronization signal powers up in a low impedance state (VOL), connect a resistor between the RT/SYNC pin and the synchronizing clock. The equivalent resistance seen from the RT/SYNC pin to ground will set the start-up frequency. If the synchronization signal powers up in a high impedance state (Hi-Z), connect a resistor from the RT/SYNC pin to ground. The equivalent resistance seen from the RT/SYNC pin to ground will set the start-up frequency.
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If the synchronization signal changes between high and low impedance states during power up (VOL, Hi-Z), connect the synchronization circuitry to the LT3500 as shown in the Typical Applications section. This will allow the LT3500 to start up with a switching frequency determined by the equivalent resistance from the RT/SYNC pin to ground. Shutdown and Undervoltage Lockout Figure 8 shows how to add an undervoltage lockout (UVLO) to the LT3500. Typically, UVLO is used in situations where the input supply is current limited, or has a relatively high source resistance. A switching regulator draws constant power from the source, so source current increases as source voltage drops. This looks like a negative resistance load to the source and can cause the source to current limit or latch low under low source voltage conditions. UVLO prevents the regulator from operating at source voltages where these problems might occur.
VIN 2.5A R1 2A SHDN C1 R2 0.76V
above the SHDN threshold. This can be used to set voltage hysteresis of the UVLO using the following: R1= R2 = VH - VL 2A 0.76 VH - 0.76 + 2.5A R1
VH = Turn-on threshold VL = Turn-off threshold Example: switching should not start until the input is above 4.75V and is to stop if the input falls below 3.75V. VH = 4.75V VL = 3.75 4.75 - 3.75 ~ 499k 2A 0.76 ~ 71.5k R2 = 4.75 - 0.76 + 2.5A 499k R1= Keep the connections from the resistors to the SHDN pin short and make sure that the interplane or surface capacitance to switching nodes is minimized. If high resistor values are used, the SHDN pin should be bypassed with a 1nF capacitor to prevent coupling problems from the switch node. Soft-Start The outputs of the LT3500 regulate to either the SS pin voltage minus 100mV or an internally regulated 800mV, whichever is lowest. A capacitor from the SS pin to ground is charged by an internal 2.75A current source resulting in a linear output ramp from 0V to the regulated output whose duration is given by: tRAMP = CSS * 0.9V 2.75A
+ -
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Figure 8. Undervoltage Lockout
An internal comparator will force the part into shutdown below the minimum VIN of 2.8V. This feature can be used to prevent excessive discharge of battery-operated systems. If an adjustable UVLO threshold is required, the SHDN pin can be used. The threshold voltage of the SHDN pin comparator is 0.76V. A 2.5A internal current source defaults the open-pin condition to be operating (see Typical Performance Characteristics). Current hysteresis is added
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At power-up, a reset signal sets the soft-start latch and discharges the SS pin to approximately 0V to ensure proper start-up. When the SS pin is fully discharged the latch is reset and the internal 2.75A current source starts to charge the SS pin. When the SS pin voltage is below 100mV, the VC pin is pulled low which disables switching. As the SS pin voltage rises above 100mV, the VC pin is released and the outputs are regulated to the SS voltage. When the SS pin voltage minus 100mV exceeds the internal 0.8V reference, the outputs are regulated to the reference. The SS pin voltage will continue to rise until it is clamped at 2V. In the event of a VIN undervoltage lockout, the SHDN pin driven below 0.8V, or the internal die temperature exceeding its maximum rating during normal operation, the soft-start latch is set, triggering a start-up sequence. In addition, if the load exceeds the maximum output switch current (switching regulator only), the output will start to drop causing the VC pin clamp to be activated. As long as the VC pin is clamped, the SS pin will be discharged. As a result, the output will be regulated to the highest voltage that the maximum output current can support. For example, if a 6V output is loaded by 1 the SS pin will drop to 0.5V, regulating the output at 3V (typical current limit time load, 3A * 1). Once the overload condition is removed, the output will soft-start from the temporary voltage level to the normal regulation point. Since the SS pin is clamped at 2V and has to discharge to 0.9V before taking control of regulation, momentary overload conditions will be tolerated without a soft-start recovery. The typical time before the SS pin takes control is: C * 1.1V t SS(CONTROL) = SS 600A Power Good Indicators The PG and PG pins are collector outputs of an internal comparator. The comparator compares the voltages of the FB and LFB pins to 90% of the reference voltage with 30mV of hysterisis. The PG pin has a sink capability of 400A when the FB and LFB pins are below the threshold and can withstand 40V when the outputs are in regulation. The PG pin is typically connected to the output with a resistor and is used as an error flag. The resistor value should be chosen to allow the PG voltage to drop below 0.4V in an error condition. Example: VOUT1 = 5V, PGSINK(MIN) = 200A RPG = (5 - 0.4)/200A = 23k The PG pin has a sink capability of 800A when the FB and LFB pins are above the threshold and can withstand 40V when the outputs are not in regulation. The PG pin is typically used as a drive signal for an output disconnect device. The PG pull-up resistor should be sized in the same manner as the PG pull-up resistor. Linear Regulator The LT3500 contains an error amplifier and a NPN output device which can be configured as a linear regulator or as a linear regulator controller. With the LFB and LDRV pins configured as shown in Figure 1, the LDRV pin outputs a regulated voltage with a typical current limit of 13mA. The LDRV voltage is programmed with a resistor divider between the output and the LFB pin. Choose the 1% resistors according to: R3 = R4 VLDRV -1 0.8V
R4 should be 10.0k or less to avoid bias current errors. Reference designators refer to the Block Diagram in Figure 1. The reference voltage for the linear regulator (LFB pin) will track the SS pin in the same manner as the FB pin of the switching regulator.
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VOUT2 AC COUPLED 20mV/DIV
LOAD STEP 2.5mA TO 7.5mA 5mA/DIV 20s/DIV
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NMOS times the output current of the regulator. This also increases the overall efficiency of the system. However, the minimum VIN increases to 2V plus the VGS at full load of the transistor. Additionally, due to a lack of beta current limiting, a shorted output can cause the switcher output of the LT3500 to collapse. Since the collector of the LDRV npn is connected internally to VIN, you must consider the impact of LDRV current on efficiency and die temperature when configuring the linear regulator/controller. For example, with VIN = 25V, LDRV = 3.3V and ILDRV = 10mA, power dissipation on the die will be 217mW. For a typical 3.3V/1A switcher application, this represents an additional 7% efficiency loss and approximately 10 degrees rise in die temperature. If the linear output of the LT3500 is not used, the LDRV pin should be shorted to the LFB Pin. PCB Layout For proper operation and minimum EMI, care must be taken during printed circuit board (PCB) layout. Figure 11 shows the high di/dt paths in the buck regulator circuit. Note that large switched currents flow in the power switch, the catch diode and the input capacitor. The loop formed by these components should be as small as possible. These components, along with the inductor and output capacitor, should be placed on the same side of the circuit board and their connections should be made on that layer. Place a local, unbroken ground plane below these components, and tie this ground plane to system ground at one location, ideally at the ground terminal of the output
D2 BAT54 4.5V TO 36V C1 2.2F VIN LT3500 SW SHDN SS FB RT/SYNC LDRV PG VC PG LFB D1 B240A R1 27.4k R2 8.06k C7 22F BST C5 L1 0.47F 3.3H
Figure 9. Linear Regulator Transient Response
To compensate the linear regulator, simply add a ceramic capacitor from the LDRV pin to ground. Typical values range from 0.01F to 1F Figure 9 illustrates the transient . response with a 0.47F output capacitor. Linear Controller By adding an external follower (NPN or NMOS), the LFB and LDRV pins can be configured as a controller (Figure 10) for a low dropout regulator with increased output capability. The output current capability of Figure 10's circuit is a product of the LDRV current limit and beta of the external NPN which is normally less than the current capability of the LT3500. The dropout voltage for the circuit is set by the saturation voltage of the external NPN, which is typically 300mV. The minimum VIN for the circuit to function properly is 2V plus the base emitter drop of the external NPN. Replacing the NPN in Figure 10 with a NMOS transistor can reduce the dropout voltage down to the RDS(ON) of the
VOUT1 3.5V
C2 0.47F
C3 220pF R6 40.2k
R3 24.9k R4 8.06k
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R5 49.9k
VOUT2 3.3V 1A C6 22F
Figure 10. Linear Controller
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VIN LT3500 SW GND VIN LT3500 SW GND VIN LT3500 SW GND
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(11a)
(11b)
(11c)
Figure 11. Subtracting the Current when the Switch is On (11a) from the Current when the Switch is Off (11b) Reveals the Path of the High Frequency Switching Current (11c). Keep this Loop Small. The Voltage on the SW and BST Traces will Also be Switched; Keep These Traces as Short as Possible. Finally, Make Sure the Circuit is Shielded with a Local Ground Plane
should be tied to other copper layers below with thermal vias; these layers will spread the heat dissipated by the LT3500. Place additional vias near the catch diodes. Adding more copper to the top and bottom layers and tying this copper to the internal planes with vias can further reduce thermal resistance. With these steps, the thermal resistance from die (or junction) to ambient can be reduced to JA = 45C/W for the DD Package, and JA = 45C/W for the MSE Package. Power dissipation within the LT3500 can be estimated by calculating the total power loss from an efficiency measurement and subtracting the catch diode loss. The die temperature is calculated by multiplying the LT3500 power dissipation by the thermal resistance from junction to ambient. The power dissipation in the other power components such as catch diodes, boost diodes and inductors, cause additional copper heating and can further increase what the IC sees as ambient temperature. See the LT1767 data sheet's Thermal Considerations section. Other Linear Technology Publications Application notes AN19, AN35 and AN44 contain more detailed descriptions and design information for buck regulators and other switching regulators. The LT1376 data sheet has a more extensive discussion of output ripple, loop compensation and stability testing. Design note DN100 shows how to generate a dual (+ and -) output supply using a buck regulator.
Figure 12. LT3500 Demonstration Circuit Board DC1069A
capacitor C2. Additionally, the SW and BST traces should be kept as short as possible. The topside metal from the DC1069A demonstration board in Figure 12 illustrates proper component placement and trace routing. Thermal Considerations The PCB must also provide heat sinking to keep the LT3500 cool. The exposed metal on the bottom of the package must be soldered to a ground plane. This ground
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23
LT3500 TYPICAL APPLICATIONS
High Efficiency Linear Regulator
D2 BAT54 4.5V TO 36V C1 2.2F VIN LT3500 SW SHDN SS FB RT/SYNC LDRV C3 220pF R6 40.2k VC R5 49.9k GND PG PG LFB R3 24.9k R4 8.06k
3500 TA02a
BST
L1 C5 0.47F 3.3H D1 B240A R1 25.5k C7 22F
C2 0.47F
R2 8.06k
R7 10k
M1 ZXMN2A03E6 VOUT2 3.3V C8 22F
Efficiency vs Load Current
90
80 EFFICIENCY (%)
70
60
50 0 0.2
0.4 0.6 0.8 1.0 1.2 LOAD CURRENT (A)
1.4
3500 TA02b
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24
LT3500 TYPICAL APPLICATIONS
5V/1.5A, 3.3V/0.5A Step-Down with Output Disconnect
D2 BAT54 6V TO 32V C1 2.2F VIN LT3500 SW SHDN SS FB RT/SYNC LDRV C3 220pF R7 40.2k VC R6 49.9k GND PG PG LFB R5 8.06k R4 24.9k
3500 TA03
BST
L1 C5 0.47F 4.7H D1 B240A R1 42.2k C7 22F R8 100k
VOUT1 5V 1.5A
C2 0.47F
R2 8.06k
Q1 ZXTCM322
VOUT2 3.3V 0.5A I89 ZXMP3A17E6
C6 22F
5V/2A Step-Down with Power Good LED
D2 BAT54 6V TO 32V C1 2.2F VIN LT3500 SW SHDN SS FB PG RT/SYNC LDRV VC R6 49.9k GND LFB PG D1 B240A R1 42.2k R2 8.06k C7 22F R8 8.06k R4 R3 42.2k 8.06k C8 1F R5 100k M1 ZXM61N02F 1
3500 TA04
BST
L1 C5 0.47F 4.7H
VOUT1 5V 2A
C2 0.47F
C3 220pF R7 40.2k
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25
LT3500 PACKAGE DESCRIPTION
DD Package 12-Lead Plastic DFN (3mm x 3mm)
(Reference LTC DWG # 05-08-1725 Rev A)
0.70 0.05
3.50 0.05 2.10 0.05
2.38 0.05 1.65 0.05 PACKAGE OUTLINE
0.25 0.05 0.45 BSC 2.25 REF RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
R = 0.115 TYP 7
0.40 0.10 12
3.00 0.10 (4 SIDES) PIN 1 TOP MARK (SEE NOTE 6)
2.38 0.10 1.65 0.10 PIN 1 NOTCH R = 0.20 OR 0.25 x 45 CHAMFER
6 0.200 REF 0.75 0.05 2.25 REF 0.00 - 0.05
0.23 0.05 0.45 BSC
(DD12) DFN 0106 REV A
1
BOTTOM VIEW--EXPOSED PAD NOTE: 1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD AND TIE BARS SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
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26
LT3500 PACKAGE DESCRIPTION
MSE Package 16-Lead Plastic MSOP Exposed Die Pad ,
(Reference LTC DWG # 05-08-1667 Rev A)
BOTTOM VIEW OF EXPOSED PAD OPTION 2.845 (.112 0.102 .004) 0.889 (.035
0.127 .005)
2.845 (.112 1
0.102 .004) 8 0.35 REF
5.23 (.206) MIN
1.651 (.065
0.102 3.20 - 3.45 .004) (.126 - .136)
1.651 (.065
0.102 .004)
0.12 REF
0.305 0.038 (.0120 .0015) TYP
0.50 (.0197) BSC
16 4.039 0.102 (.159 .004) (NOTE 3)
DETAIL "B" CORNER TAIL IS PART OF DETAIL "B" THE LEADFRAME FEATURE. FOR REFERENCE ONLY 9 NO MEASUREMENT PURPOSE
RECOMMENDED SOLDER PAD LAYOUT
16151413121110 9
0.280 0.076 (.011 .003) REF
0.254 (.010) GAUGE PLANE
DETAIL "A" 0 - 6 TYP 4.90 0.152 (.193 .006) 3.00 0.102 (.118 .004) (NOTE 4)
0.53 0.152 (.021 .006) DETAIL "A" 0.18 (.007) 12345678 1.10 (.043) MAX 0.86 (.034) REF
SEATING PLANE
NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.17 -0.27 (.007 - .011) TYP
0.50 (.0197) BSC
0.1016 (.004
0.0508 .002)
MSOP (MSE16) 0608 REV A
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LT3500 TYPICAL APPLICATION
1.8V/2A Step-Down Regulator
4.5V TO 36V C1 2.2F VIN LDRV LT3500 LFB C2 R5 0.47F 40.2k C3 220pF SHDN SS BST C5 0.47F RT/SYNC SW FB VC PG PG D1 L1 2.2H R1 10k R2 8.06k VOUT1 1.8V 2A C7 22F
3500 TA05
R3 R4 24.9k 8.06k
C6 1F
VOUT2 3.3V 10mA D2
R6 49.9k
RELATED PARTS
PART NUMBER LT1766 LT1933 LT1936 LT1940 LTC3407/LTC3407-2 LT3434/LT3435 LT3437 LT3493 LT3501 LT3502/LT3502A LT3503 LT3505 LT3506/LT3506A LT3508 LT3510 LTC3548 LT3680 DESCRIPTION 60V, 1.2A (IOUT), 200kHz High Efficiency Step-Down DC/DC Converter 36V, 500mA (IOUT), 500kHz Step-Down Switching Regulator in SOT-23 36V, 1.4A (IOUT), 500kHz High Efficiency Step-Down DC/DC Converter Dual 25V, 1.4A (IOUT), 1.1MHz High Efficiency Step-Down DC/DC Converter Dual 600mA/800mA, 1.5MHz/2.25MHz Synchronous Step-Down DC/DC Converter 60V, 2.4A (IOUT), 200kHz/500kHz High Efficiency Step-Down DC/DC Converters with Burst Mode Operation 60V, 400mA (IOUT), Micropower Step-Down DC/DC Converter with Burst Mode Operation 36V, 1.4A (IOUT), 750kHz High Efficiency Step-Down DC/DC Converter Dual 25V, 3A (IOUT), 1.5MHz High Efficiency Step-Down DC/DC Converter 40V, 500mA (IOUT), 1.1MHz/2.2MHz High Efficiency Step-Down DC/DC Converter COMMENTS VIN: 5.5V to 60V, VOUT(MIN) = 1.20V, IQ = 2.5mA, ISD = 25A, 16-Lead TSSOPE Package VIN: 3.6V to 36V, VOUT(MIN) = 1.2V, IQ = 1.6mA, ISD < 1A, ThinSOTTM Package VIN: 3.6V to 36V, VOUT(MIN) = 1.2V, IQ = 1.9mA, ISD < 1A, 8-Lead MS8E Package VIN: 3.6V to 25V, VOUT(MIN) = 1.20V, IQ = 3.8mA, ISD < 30A, 16-Lead TSSOPE Package VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 40A, ISD < 1A, 3mm x 3mm DFN and 10-Lead MS10E Packages VIN: 3.3V to 60V, VOUT(MIN) = 1.20V, IQ = 100A, ISD < 1A, 16-Lead TSSOPE Package VIN: 3.3V to 60V, VOUT(MIN) = 1.25V, IQ = 100A, ISD < 1A, 10-Lead 3mm x 3mm DFN, 16-Lead TSSOPE Package VIN: 3.6V to 36V, VOUT(MIN) = 0.8V, IQ = 1.9mA, ISD < 1A, 6-Lead 2mm x 3mm DFN Package VIN: 3.3V to 25V, VOUT(MIN) = 0.8V, IQ = 3.7mA, ISD < 10A, 20-Lead TSSOPE Package VIN: 3V to 40V, VOUT(MIN) = 0.8V, IQ = 1.5mA, ISD < 2A, 8-Lead 2mm x 2mm DFN Package
20V, 1A (IOUT), 2.2MHz High Efficiency Step-Down DC/DC Converter VIN: 3.6V to 20V, VOUT(MIN) = 0.78V, IQ = 1.9mA, ISD < 1A, 6-Lead 2mm x 3mm DFN Package 36V, 1.2A (IOUT), 3MHz High Efficiency Step-Down DC/DC Converter VIN: 3.6V to 36V, VOUT(MIN) = 0.78V, IQ = 2mA, ISD < 2A, 8-Lead 3mm x 3mm DFN and MSE Packages Dual 25V, 1.6A (IOUT), 575kHz/1.1MHz High Efficiency Step-Down DC/DC Converters Dual 36V, 1.4A (IOUT), 2.5MHz High Efficiency Step-Down DC/DC Converter Dual 25V, 2A (IOUT), 1.5MHz High Efficiency Step-Down DC/DC Converter Dual 400mA/800mA, 2.25MHz Synchronous Step-Down DC/DC Converter 36V, 3.5A (IOUT), 2.4MHz High Efficiency Step-Down DC/DC Converter VIN: 3.6V to 25V, VOUT(MIN) = 0.8V, IQ = 3.8mA, ISD < 30A, 16-Lead 4mm x 5mm DFN and TSSOPE Packages VIN: 3.6V to 36V, VOUT(MIN) = 0.8V, IQ = 4.3mA, ISD < 1A, 24-Lead 4mm x 4mm QFN and 16-Lead TSSOPE Packages VIN: 3.3V to 25V, VOUT(MIN) = 0.8V, IQ = 3.7mA, ISD < 10A, 20-Lead TSSOPE Package VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 40A, ISD < 1A, 3mm x 3mm DFN and 10-Lead MSE Packages VIN: 3.6V to 36V, VOUT(MIN) = 0.79V, IQ = 75A, ISD < 1A, 3mm x 3mm DFN and MS10E Packages
3500fb LT 1008 REV B * PRINTED IN USA
ThinSOT is a trademark of Linear Technology Corporation
28 Linear Technology Corporation
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